1. Field of the Invention
The present invention relates to a sequential logic circuit and more particularly, to a sequential logic circuit equipped with a latch circuit having active and sleep modes.
2. Description of the Prior Art
In recent years, semiconductor integrated logic devices have been designed to cope with both high-speed operation in the active mode and low power-dissipation in the sleep mode. The "active mode" is the state where the normal operation of the logic devices are performed. The "sleep mode" is the state where the normal operation of the logic devices are stopped. The "sleep mode" may be termed the "power-down mode" because of its purpose of reducing the power dissipation. It is important for the semiconductor integrated logic devices of this sort to prevent the stored information in the devices from being broken especially in the sleep mode.
An example of the prior-art semiconductor integrated logic devices of this sort is disclosed in the Japanese Non-Examined Patent Publication No. 7-271477 published in October 1995. This semiconductor integrated logic device, which is shown in FIG. 15 of this Publication, is formed by Metal-oxide-semiconductor Field-Effect Transistors (MOSFETs) whose threshold voltage is low (i.e., low-threshold MOSFETs) and is operated at a low power supply voltage.
MOSFETs having the low threshold voltage have a characteristic that the subthreshold current (i.e., current leakage) flowing between the source and drain during the OFF state is comparatively large. Therefore, an upper-side power supply and a lower-side power supply are connected to the logic circuits through MOSFETs whose threshold voltage is high (i.e., high-threshold MOSFETs). This is because high-threshold MOSFETs have low current leakage during the OFF state. Moreover, a bistable circuit formed by high-threshold MOSFETs is added to the logic circuit. The bistable circuit is directly supplied with a power supply. Thus, the subthreshold leakage current is prevented in the sleep mode and at the same time, the information stored in the logic circuit is prevented from being broken or lost.
Furthermore, with the prior-art semiconductor integrated logic device, when the sleep mode is finished, the logic device is supplied with the upper- and lower-side power supplies again and then, the instruction for holding the clock signal is canceled. At the start of the sleep mode, the clock signal is shifted to its holding state and then, the logic circuit is shifted from the active mode to the sleep mode.
Next, the above-described prior-art semiconductor integrated logic device disclosed in the Japanese Non-Examined Patent Publication No. 7-271477 is explained in detail with reference to FIG. 1.
As shown in FIG. 1, this prior-art logic circuit is comprised of a latch circuit FF102 having set and reset functions. The latch circuit FF102 includes two transmission gates TM1 and TM2, three inverters INV101, INV102, and INV103, and a NOR gate NOR101.
The inverter INV101 has a p-channel MOSFET having a low threshold voltage (i.e., low-threshold p-channel MOSFET) (not shown) and a low-threshold n-channel MOSFET (not shown). The gates of these two MOSFETs are coupled together to be connected to an input terminal of the inverter INV101 to which a data signal D is applied. The drains of these two MOSFETs are coupled together to be connected to an output terminal of the inverter INV101 from which an output signal D1 is derived. The source of the p-channel MOSFET is connected to an upper-side power supply of V.sub.DD through a high-threshold p-channel control MOSFET HP101. The source of the n-channel MOSFET is connected to a lower-side power supply (i.e., the ground potential GND) through a high-threshold n-channel control MOSFET HN101. The output signal D1 of the inverter INV101 is applied to a bidirectional terminal of the transmission gate TM101. Thus, the inverter INV101 is formed by the low-threshold MOSFETs and therefore, it is capable of high-speed operation.
The high-threshold MOSFET HP101 serves to connect the inverter 101 to the upper-side power supply of V.sub.DD or disconnect the inverter 101 therefrom in response to a sleep mode signal SL. Similarly, the high-threshold MOSFET HN101 serves to connect the inverter 101 to the ground GND or disconnect the inverter 101 therefrom in response to an inverted sleep mode signal SLB. The signal SLB has an inverted value to that of the signal SL.
To enter the sleep mode, the sleep mode signal SL is in the logic high (H) level (i.e., SL=1) and the inverted sleep mode signal SLB is in the logic low (L) level (i.e., SLB=0). At this stage, the control transistors HP101 and HN101 are turned off, blocking the supply of the supply voltage V.sub.DD and the ground potential GND to the inverter INV101. Since the control transistors HP101 and HN101 have the high threshold voltages, they have small subthreshold leakage currents, which decreases the power consumption in the sleep mode.
The transmission gate TM101 has a low-threshold p-channel MOSFET (not shown) and a low-threshold n-channel MOSFET (not shown). The drain and source of the p-channel MOSFET are connected to the source and drain of the n-channel MOSFET, respectively. The gate of the n-channel MOSFET is applied with a clock signal .phi.. The gate of the p-channel MOSFET is applied with an inverted clock signal *.phi.. The signal *.phi. has an inverted value to that of the signal .phi.. One of the bidirectional terminals of the transmission gate TM101 is connected to the output terminal of the inverter INV101 and the other is connected to a second input terminal of the NOR gate NOR101.
As described above, the NOR gate NOR101 is formed by the low-threshold MOSFETs and therefore, it is capable of high-speed operation.
The NOR gate NOR101 has first and second low-threshold p-channel MOSFETs (not shown) and first and second low-threshold n-channel MOSFETs (not shown). The first and second -channel MOSFETs are connected in series to form two terminals, one of which is applied with the power supply voltage V.sub.DD and the other is connected to an output terminal of the NOR gate NOR101. The gate of the first p-channel MOSFET, which is connected to a first input terminal of the gate NOR101, is applied with a reset signal RT. The gate of the second p-channel MOSFET, which is connected to the second input terminal of the gate NOR101, is applied with the output signal D2 from the transmission gate TM101. The first and second n-channel MOSFETs are connected in parallel to form two terminals, one of which is connected to the ground GND and the other is connected to the output terminal of the NOR gate NOR101. The gate of the first n-channel MOSFET, which is connected to the first input terminal of the gate NOR101, is applied with the reset signal RT. The gate of the second n-channel MOSFET, which is connected to the second input terminal of the gate NOR101, is applied with the output signal D2 from the transmission gate TM101.
The output signal D3 of the NOR gate NOR101, which is the result of the NOR operation between the signal D2 and the reset signal RT, is outputted as an output signal Q from an output terminal of the latch circuit FF102 to a next-stage circuitry (not shown). At the same time as this, the signal D3 is further applied to the inverter INV102.
Since the NOR gate NOR101 is formed by the low-threshold MOSFETs, it is capable of high-speed operation.
The NOR gate NOR101 is supplied with the upper-side power supply of V.sub.DD through a high-threshold p-channel control MOSFET HP102 and with the ground potential GND through a high-threshold n-channel control MOSFET HN102. The high-threshold MOSFET HP102 serves to connect the gate NOR101 to the power supply of V.sub.DD or disconnect the inverter 101 therefrom in response to the sleep mode signal SL. Similarly, the high-threshold MOSFET HN102 serves to connect the gate NOR101 to the ground GND or disconnect the gate NOR101 therefrom in response to the inverted sleep mode signal SLB.
In the sleep mode where the signal SL is in the logic H level (i.e., SL=1) and the inverted sleep mode signal SLB is in the logic L level (i.e., SLB=0), the control transistors HP102 and HN102 are turned off, blocking the supply of the supply voltage V.sub.DD and the ground potential GND to the NOR gate NOR101. Since the control transistors HP102 and HN102 have the high threshold voltages, they have small subthreshold leakage currents, which decrease the power consumption.
The inverter INV102 has a high-threshold p-channel MOSFET (not shown) and a high-threshold n-channel MOSFET (not shown). The gates of these two MOSFETs are coupled together to be connected to the output terminal of the latch circuit FF102 from which the output signal Q is derived. Therefore, these gates are applied with the signal Q. The drains of these two MOSFETs are coupled together to be connected to an output terminal of the inverter INV102 from which an output signal D4 is derived. The source of the p-channel MOSFET is connected to the power supply of V.sub.DD. The source of the n-channel MOSFET is connected to the ground potential GND. The output signal D4 of the inverter INV102 is applied to a bidirectional terminal of the transmission gate TM102. Thus, the inverter INV102 is formed by the high-threshold MOSFETs and therefore, it is capable of decreasing the power consumption in the sleep mode.
To distinguish the inverter INV102 comprising the high-threshold MOSFETs from the inverter INV101 comprising the low-threshold MOSFETs, hatching is added to the symbol of the inverter INV102 in FIG. 1.
The transmission gate TM102 has a low-threshold p-channel MOSFET (not shown) and a low-threshold n-channel MOSFET (not shown). The gate TM102 has the same configuration as that of the transmission gate TM101 except that the gate of the n-channel MOSFET is applied with the inverted clock signal *.phi. and the gate of the p-channel MOSFET is applied with the clock signal .phi.. One of the bidirectional terminals of the transmission gate TM102 is connected to the output terminal of the inverter INV102 and the other is connected to the second input terminal of the NOR gate NOR101.
As described above, the NOR gate NOR102 is formed by the low-threshold MOSFETs and therefore, it is capable of high-speed operation.
To control the information-storing or latch function of the latch circuit FF102, the latch circuit FF102 includes an inverter INV103 connected in parallel to the NOR gate NOR101. The inverter INV103 has the same configuration as that of the inverter INV102. The inverter INV103 is also formed by high-threshold MOSFETs and therefore, it is capable of decreasing the power consumption in the sleep mode. To distinguish the inverter INV103 from the inverter INV101, hatching is added to the symbol of the inverter INV103 in FIG. 1.
Next, the operation of the latch circuit FF102 having the above-described configuration is explained below with reference to FIGS. 2A to 2E.
The latch circuit FF102 enters the active mode when the sleep mode signal SL is in the logic L level (i.e., SL=0) and the inverted sleep mode signal SLB is in the logic H level (i.e., SLB=1). In this mode, the control transistors HP101, HN101, HP102, and HN102 are turned on, allowing the supply voltage V.sub.DD and the ground potential GND to be supplied to the inverter INV101 and the NOR gate NOR101. Therefore, the inverter INV101 is capable of its inverting operation with respect to the data signal D, and the gate NOR101 is capable of its NOR operation with respect to the output signal D2 of the transmission gate TM101.
When the reset signal RT is in the logic L level (i.e., RT=0), the latch circuit FF102 is not reset and capable of its high-speed latch operation. In this state, the output signal D1 of the inverter INV101 is introduced by the opened transmission gate TM101 at the time t1 when the pulse of the clock signal .phi. is rising (i.e., the pulse of the inverted clock signal *.phi. is falling) and then, the signal D1 is transmitted to the NOR gate NOR101 and the inverter INV103. At this time t1, as shown in FIG. 2C, the clock signal .phi. is turned from the latch mode to the through mode. After a latch release time tPD1 is passed (see FIG. 2A), the inverter INV103 outputs the output signal D3' as the output signal Q of the latch circuit FF102 at the time t2.
At this stage, the transmission gate TM102 is closed at the time t1 by the inverted clock signal *.phi.. Therefore, the output signal D2 of the inverter INV101 and the output signal D4 of the inverter INV102 do not become competitive.
If the logic state of the data signal D is inverted at the time t3 during the through mode of the clock signal .phi., as shown in FIG. 2B, the inversion of the signal D appears in the output signal Q at the time t4 delayed by a propagation delay time tPD2 with respect to the time t3, as shown in FIG. 2A. To ensure the normal operation of the latch circuit FF2, the inversion of the signal D is possible under the condition that the inversion time t3 of the clock signal .phi. is prior to the inversion time t4 of the data signal D by at least a set-up time tDS. Also, the inverted data signal D needs to be held by the time t5 delayed by a data hold time tDH with respect to the time t4, as shown in FIG. 2B.
Then, the data signal D introduced by the transmission gate TM101 is inputted into the inverter INV102 through the NOR gate NOR101 and the inverter INV103. Furthermore, the data signal D is introduced by the transmission gate TM102 at the time t4 and then, it is fed back to the second input terminal of the NOR gate NOR101 and the input of the inverter INV103.
At this stage, the transmission gate TM101 is closed at the time t4 and therefore, the output signal D5 of the transmission gate TM102 and the output signal D2 of the inverter INV102 do not become competitive.
If the reset signal RT in the logic H level (i.e., RT=1) is applied to the latch circuit FF102 during the active mode (i.e., SL=0 and SLB=1), the output signal Q is forced to be turned to the logic L level (i.e., Q=0) independent of the state of the clock signal .phi. and the inverted clock signal *.phi.. Thus, the reset operation of the latch circuit FF102 is carried out.
As explained above, in the active mode where the sleep mode signal SL is in the logic L level (SL=0) and the inverted sleep mode signal SLB is in the logic H level (SLB=1), the control MOSFETs HP101, HN101, HP102, and HN102 conduct are in the ON state, allowing the power supply voltage V.sub.DD and the ground potential GND to be supplied to the MOSFETs HP101, HN101, HP102, and HN102. This means that both the inverter INV101 and the NOR gate NOR101 are operable in the active mode. As a result, the data signal D is latched by the latch circuit FF102 according to the clock signal .phi. and the inverted clock signal *.phi.. In other words, the latch circuit FF102 has a high-speed latch operation.
Next, the operation of the latch circuit FF102 in the sleep mode is explained below with reference to FIGS. 2A to 2E.
The latch circuit FF102 enters the sleep mode when the sleep mode signal SL is in the logic H level (i.e., SL=1) and the inverted sleep mode signal SLB is in the logic L level (i.e., SLB=0). In this mode, the control transistors HP101, HN101, HP102, and HN102 are turned off, blocking the supply of the power supply voltage V.sub.DD and the ground potential GND to the inverter INV101 and the NOR gate NOR101. Therefore, the inverter INV101 is unable to perform its inverting operation with respect to the data signal D, and the gate NOR101 is unable to perform its NOR operation with respect to the output signal D2 of the transmission gate TM101.
The operation of the latch circuit FF102 in the sleep mode is explained in detail below.
Here, prior to the transition from the active mode (i.e., SL=0 and SLB=1) to the sleep mode (i.e., SL=1 and SLB=0), it is assumed that the clock signal .phi. is fixed in the logic L level (i.e., .phi.=0) and the inverted clock signal *.phi. is fixed in the logic H level (i.e., *.phi.=1). Also, it is assumed that the clock signal .phi. in the logic L level and the inverted clock signal *.phi. in the logic H level are kept unchanged in the sleep mode. This is to ensure the latch operation of the circuit FF102. Specifically, the inverters INV102 and INV103, which are connected to each other through the transmission gate TM102, constitute a bistable circuit. Therefore, the inputted data to the latch circuit FF102 immediately before the transition to the sleep mode can be latched by the bistable circuit.
To ensure the latch operation in the sleep mode, it is needless to say that the power supply voltage V.sub.DD and the ground potential GND are kept being supplied to the inverters INV102 and INV103 even in the sleep mode. Since the inverters INV102 and INV103 are formed by the high-threshold MOSFETs, current leakage is small in the sleep mode, resulting in low power consumption of the inverters INV102 and INV103. On the other hand, the supply of the power supply voltage V.sub.DD and the ground potential GND to the inverter INV101 and the NOR gate NOR101 is stopped and at the same time, the control MOSFETs HP101, HN101, HP102, and HN102 have the high threshold voltage. Thus, current leakage is small in the sleep mode, resulting in low power consumption of the MOSFETs HP101, HN101, HP102, and HN102.
Next, the conditions for satisfying the above-described assumption that the clock signal .phi. is fixed in the logic L level (i.e., .phi.=0) and the inverted clock signal *.phi. is fixed in the logic H level (i.e., *.phi.=1) and that the clock signal .phi. in the logic L level and the inverted clock signal *.phi. in the logic H level are kept unchanged in the sleep mode are explained below.
When the operation of the latch circuit FF102 is turned from the active mode to the sleep mode, the logic state (L or H) of the data signal D needs to be held at the time t5 subsequent to the time t4 when the circuit FF102 is turned to the latch mode by at least the data hold time tDH.
On the other hand, if the latch circuit FF102 is incorporated into a semiconductor integrated logic circuit including sequential logic circuits similar to the circuit FF102 and combinational logic circuits, the necessary time for the data hold times to be passed in all the sequential logic circuits including the latch circuit FF102 is longer than the data hold time tDH due to the different propagation delays of signals. Considering this fact, the transition from the active mode to the sleep mode needs to be performed at the time t6 after a release time tRL0 is passed from the time t5.
Additionally, at the time t7 after a data calm time tDC from the time t6, the data signal D is turned to be in a floating or undefined state. Similarly, at the time t7 after a reset calm time tRC from the time t6, the reset signal RT is also turned to be in a floating or undefined state. The floating or undefined state of the signals D and RT are held through the sleep mode. Also, to keep the stored data in the latch circuit FF102 through the sleep mode, in other words, to keep the bistable circuit formed by the inverters INV102 and INV103 active, the transmission gate TM102 needs to be kept conductive (i.e., ON). Therefore, the clock signal .phi. in the logic L level and the inverted clock signal *.phi. in the logic H level are required to be kept unchanged. Moreover, the stored value of the output signal Q of the latch circuit FF102 in the sleep mode is kept unchanged because the inverter INV103 is kept active.
Next, the transition from the sleep mode to the active mode after the sleep mode has been held for a specific period is explained below.
To return the operation of the latch circuit FF102 from the sleep mode to the active mode, the logic state of the sleep signal SL is turned from the H level to the L level at the time t8. At this stage, the logic state (L or H) of the data signal D is returned to the prior state just before entering the sleep mode at the time t10. The time t10 is delayed from the time t8 by a data recovery time tDB. Similarly, the logic state (L or H) of the reset signal RT is returned to the prior state just before entering the sleep mode at the time t10. The time t10 is delayed from the time t8 by a reset recovery time tRB.
On the other hand, as already described above, if the latch circuit FF102 is incorporated into a semiconductor integrated logic circuit including sequential logic circuits similar to the circuit FF102 and combinational logic circuits, the necessary time for the data and reset recovery times to be passed in all the sequential logic circuits including the latch circuit FF102 is longer than the data recovery time tDB and the reset recovery time tRB due to the different propagation delays of signals. Considering this fact, the transition of the data and reset signals D and RT need to be performed at the time t11 after a removal time tRM0 is passed from the time t10. Needless to say, the fact that the data signal D is shifted at the time t11 prior to the time t12 by a set-up time tDS should be considered. At the time t12, the clock signal .phi. is turned from the latch mode to the through mode.
With the prior-art sequential logic circuit or latch circuit FF102 shown in FIG. 1, however, there is a problem the value or information of the stored signal D is broken immediately after the transition from the sleep mode to the active mode. This problem is caused by the following reason.
As explained previously, at the time t10, which is delayed from the time t8 by the data recovery time tDB, the logic state (L or H) of the reset signal RT is returned to the prior state just before entering the sleep mode (i.e., the reset signal RT is in the logic L state, or RT=0). This is due to the different propagation delays of the signals. At the time t8, the instruction to return from the sleep mode to the active mode is performed.
Therefore, immediately after the transition instruction by the sleep signal SL at the time t8, the control MOSFETs HP101, HN101, HP102, and HN102 are in the ON state by the sleep signal SL in the logic L state (i.e., SL=0) and the inverted sleep signal SLB in the logic H state (i.e., SLB=1). Thus, the supply voltage V.sub.DD and the ground potential GND are supplied to the inverter INV101 and the NOR gate NOR101. This means that the inverter INV101 and the NOR gate NOR101 have been already operable immediately after the time t8.
Accordingly, the reset signal RT in the floating or undefined logic state is outputted by the NOR gate NOR101 as the output signal Q in the floating or undefined logic state. The undefined output signal Q thus produced is then sent to the inverter INV103 and the NOR gate NOR101 through the inverter INV102 and the conducting transmission gate TM102. Finally, the undefined output signal Q is fed back to the inverter INV102, breaking the stored signal or information in the inverter INV102.